Selector in switching matrix, line redundant method, and line redundant system

ABSTRACT

There is provided a line redundant method for implementation of line switching in a switching matrix, including the bridge step of outputting a data signal to a plurality of redundant lines in the switching matrix, and the selector step of selecting only a data signal, of a plurality of data signals input from another switching matrix other than the switching matrix through the plurality of redundant lines, which is input through a redundant line required in the switching matrix, and not selecting the data signals input to the switching matrix through the lines other than the required redundant line. A line redundant system for implementing this method is also provided.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a selector, line redundant method, andline redundant system which realize line switching in a switching matrixto recover from line troubles and the like and, more particularly, to aline redundant scheme which has a simple hardware arrangement and allowsline switching on a port basis.

2. Description of the Prior Art

Recently, demands have arisen for an improvement in the reliability ofan ATM (Asynchronous Transfer Mode) switching network with respect toline troubles. As a line redundant scheme in a case wherein ATMswitching is realized on a SONET (Synchronous Optical Network) or SDH(Synchronous Digital Hierarchy) network, an APS (Automatic ProtectionSwitching)-scheme is available, in which when a failure occurs in aWorking route (Working Connection), the route is automatically switchedto a protection route (Protection Connection) to continue thecommunication. As standards for this scheme, Bellcore (BellCommunications Research) standards, ANSI (American National StandardsInstitute) T1.105.01-1998, ITU-T (International TelecommunicationUnion-Telecommunication Standardization Sector) G.783, and the like aredefined.

There are two types of switching control schemes in APS, namely aphysical layer scheme using K1/K2 bytes on a SONET framer as controlinformation for the opposite side and an ATM layer scheme using an OAM(Operation Administration and Maintenance) cell called an APS cell ascontrol information for the opposite side.

The physical layer scheme includes two types of schemes, namely a (1+1)scheme and (1:1) scheme. In this case, in the (1+1) scheme, on thetransmission side, a data signal is copied, and the identical datasignals are simultaneously sent out to the two connections, i.e., theworking route and protection route. On the reception side, the datasignal is normally received through the working route. When a troubleoccurs on the working route, only the connection on the reception sideis switched from the working route to the protection route, therebycontinuing the communication of a main data signal.

In the (1:1) scheme, on the transmission side, a main data signal andsub-data signal are respectively received through the working route andprotection route. On the reception side, data signals from the tworoutes are normally received through the respective routes. When atrouble occurs on the working route, the connection is switched from theworking route to the protection route on both the sides, i.e., thetransmission side and reception side, thereby continuing thecommunication of the main data signal.

Of the above two types of physical layer schemes, the (1+1) scheme towhich the present invention is applied requires a bridge function ofdistributing a data signal sent to the working route on the transmissionside to the protection route as well, a selector function of cutting offa data signal, of data signals input to a switch on the reception side,which is sent from the protection route, and a function of performingline switching control on a port on the opposite side by using K1/K2bytes on a SONET frame.

For example, a conventional arrangement for a line redundant system forrealizing APS is disclosed in Japanese Unexamined Patent ApplicationPublication (KOKAI) No. 9-275405. In an embodiment in this reference,the arrangement of a dual redundant system in an ATM switch isdescribed. A selector (input cutoff circuit) and bridge (output-sidedistribution circuit) exist on a common switching fabric.

The operation of this conventional system will be described below withreference to FIGS. 1, 2, and 3.

FIG. 1 shows an example of the overall arrangement of the system in acase wherein terminals 1 and 4 communicate with each other. Theterminals 1 and 4 communicate with each other through ATM switchingmatrixes 2 and 3. Dual transmission paths are set between the ATMswitching matrixes 2 and 3 by APS based on the (1+1) scheme. Dottedlines 16 indicate the flows of data signals sent out from the terminal 1to the terminal 4. Note that in FIG. 1, an illustration of the flows ofdata signals from the terminal 4 to the terminal 1 is omitted.

FIG. 2 shows the detailed arrangements of a common switching fabric 13a, 0-system line accommodating section 30 a-0, and 1-system lineaccommodating section 40 a-1 of the ATM switching matrix 2 shown inFIG. 1. Note that FIG. 2 also shows the arrangement of a portion whichreceives data signals to be sent from the terminal 4 to the terminal 1.

FIG. 3 is a block diagram showing the detailed arrangement of the ATMswitching matrix 3 in APS operation. In this case, the internalarrangement of the ATM switching matrix 3 is the same as that of the ATMswitching matrix 2, and the letter added to the end of the referencenumeral of each component is changed from a to b. The 0/1-system lineaccommodating sections 30 a-0 and 40 a-1 of the ATM switching matrix 2are respectively connected to 0/1-system line accommodating sections 30b-0 and 40 b-1 of the ATM switching matrix 3. A selector 19 b in FIG. 3exhibits a state after APS operation; the selector 19 b selects anoutput from the 1-system line accommodating section 40 b-1 and cuts offan output from the 0-system line accommodating section 30 b-0.

As is obvious from FIGS. 1 and 2, the data signal transmitted from theterminal 1 is input to the ATM switching matrix 2 through a lineaccommodating section 12 a and bridged (distributed) to the 0-systemline accommodating section 30 a-0 and 1-system line accommodatingsection 40 a-1 by the common switching fabric 13 a. The resultantsignals are then output to a working route 14 and protection route 15,respectively.

As is obvious from FIGS. 1 and 3, the data signal input from the workingroute 14 to the ATM switching matrix 3 arrives at the terminal 4 throughthe 0-system line accommodating section 30 b-0, a common switchingfabric 13 b, and a line accommodating section. 12 b. On the other hand,the data signal input from the protection route 15 to the ATM switchingmatrix 3 is input to the common switching fabric 13 b through the1-system line accommodating section 40 b-1, but the output to the lineaccommodating section 12 b is cut off by the selector (19 b in FIG. 3)in the common switching fabric 13 b.

The detailed arrangement of a conventional APS scheme will be describedwith reference to FIG. 2. Assume that a general technique is used as aswitching control function using K1/K2 bytes. A description about thedetection of a trouble in the working route and the exchange of controlinformation with opposite ports by using K1/K2 bytes after the detectionwill therefore be omitted.

Referring to FIG. 2, the ATM switching matrix 2 is constituted by thecommon switching fabric 13 a, the 0-system line accommodating section 30a-0, the 1-system line accommodating section 40 a-1, and an OS(Operating System) 50 a. The line accommodating sections are comprisedof transmission/input interfaces (to be referred to as line IFshereinafter) 32 a and 33 a (0-system side) and 42 a and 43 a (1-systemside), output ports 34 a-1 to 34 a-N (0-system side) and 44 a-1 to 44a-N (1-system side) for accommodating a plurality of lines (N lines foreach line IF in FIG. 2), input ports 35 a-1 to 35 a-N (0-system side)and 45 a-1 to 45 a-N (1-system side), and line control sections 31 a and41 a which perform APS control, together with the OS 50 a, by usingopposite ports and K1/K2 bytes of SONET frames in APS operation.

The output ports 34 a-1 to 34 a-N and 44 a-1 to 44 a-N and input ports35 a-1 to 35 a-N and 45 a-1 to 45 a-N are constituted by an opticalmodule (not shown), a framer (not shown) for interfacing between aphysical layer and an ATM layer, and the like. The respective pairs of0/1-system transmission/input ports in the 0-system line accommodatingsection 30 a-0 and 1-system line accommodating section 40 a-1 areconnected to switch IFs 17 a-1 to 17 a-n to realize a redundantarrangement.

For example, referring to FIG. 2, each of the pairs of output ports (34a-1 and 44 a-1), . . . , (34 a-N and 44 a-N) and of input ports (35 a-1and 45 a-1), . . . , (35 a-N and 45 a-N) has an APS redundantarrangement.

The common switching fabric 13 a is comprised of a switch core 16 a,switch IFs 17 a-1 to 17 a-n, and switch control section 80 a. The switchcore 16 a has 2n interfaces on the transmission/reception side for theswitch IFs 17 a-1 to 17 a-n and switches ATM cells from the respectiveswitch IFs. The switch IFs 17 a-1 to 17 a-n connect the interfaces ofthe common switching fabric 13 a to the 0/1-system line accommodatingsections in pairs. The switch control section 80 a controls the dualredundant arrangement in cooperation with the OS 50 a.

A bridge 18 a and selector 19 a are accommodated in the switch IFs 17a-1 to 17 a-n. The bridge 18 a has a function of simultaneouslydistributing a data signal from the switch core 16 a to the 0-systemline accommodating section 30 a-0 to the 1-system line accommodatingsection 40 a-1. The selector 19 a has a cutoff function of inhibiting anunselected data signal from being input to the switch core 16 a byselecting one of the 0/1-system line accommodating section pair 30 a-0and 40 a-1.

As is obvious from the detailed arrangement of the ATM switching matrix3 in FIG. 3, the following problems arise when a plurality of outputports 34 b-1 to 34 b-N and 44 b-1 to 44 b-N and input ports 35 b-1 to 35b-N and 45 b-1 to 45 b-N are accommodated on the plurality of lineaccommodating sections 30 b-0 and 40 b-1 a predetermined number of portsat a time, and a selector 19 b (input cutoff circuit) exists in theswitch IF 17 b-1 in the common switching fabric 13 b.

Even when only switching from the input port 35 b-1 in the 0-system lineaccommodating section 30 b-0 on the working route to the input port 45b-1 in the 1-system line accommodating section 40 b-1 on the protectionroute is to be performed, since the selector 19 b exists in the commonswitching fabric 13 b, switching cannot be done on a input port basis.Hence, switching is done on a line accommodating section basis. As aconsequence, the remaining input ports 35 b-2 (not shown) to 35 b-N innormal operation in the 0-system line accommodating section 30 b-0 arealso switched to the input orts 45 b-2 (not shown) to 45 b-N in the1-system line accommodating section 40 b-1. When such switching occurs,cell loss may occur in the input ports 35 b-2 (not shown) to 35 b-Nwhich are normally operated.

In addition, since switching from the working route to the protectionroute is performed by the selector 19 b, selectors 19 b must be providedfor all the switch IFs 17 b-1 to 17 b-n in the common switching fabric13 b. Consequently, the internal hardware arrangement of the commonswitching fabric 13 b is complicated.

SUMMARY OF THE INVENTION

The present invention has been made in view of the foregoingcircumstances in the prior art, and has for its object to provide a lineredundant method which performs line switching based on the (1+1) APSscheme on a port basis by using a selector having a cutoff function ofoutputting/not outputting one data signal of a plurality of data signalsinput from a switching matrix, and a line redundant system forimplementing the method.

In order to achieve the above object, according to the first aspect ofthe present invention, there is provided a line redundant method,comprising:

the bridge step of outputting a data signal to a plurality of redundantlines in a switching matrix; and

the selector step of selecting only a data signal, of a plurality ofdata signals input from another switching matrix other than theswitching matrix through the plurality of redundant lines, which isinput through a redundant line required in the switching matrix, and notselecting the data signals input to the switching matrix through thelines other than the required redundant line.

In the first aspect, the selector step is implemented by using a framerfunction for the data signal.

In order to realize the above object, according to the second aspect ofthe present invention, there is provided a line redundant system,comprising:

bridge means for simultaneously outputting data signals to a pluralityof grouped line accommodating sections connected to a common switchingfabric in a switching matrix, and selector means for outputting only adata signal, of data signals input from another switching matrix otherthan the switching matrix to a plurality of grouped input ports in theline accommodating sections, which is required in the common switchingfabric from the input port to the common switching fabric, and cuttingoff the data signals from other input ports other than the input port.

In the second aspect, the selector means is implemented by using aframer provided for the input port.

With the above arrangement, when line switching is performed by the(1+1) APS scheme, the selector function of cutting off a data signaloutput from a line accommodating section in the protection route to thecommon switching fabric can be implemented on a port basis. Thiseliminates the necessity of switch the remaining input ports duringnormal operation in the same line accommodating section, and henceprevents the occurrence of cell loss due to switching.

In addition, since each switch IF in the common switching fabric needsnot have a selector, the hardware arrangement of the common switchingfabric can be simplified as compared with the conventional schemes.

The above and many other objects, features and advantages of the presentinvention will become manifest to those skilled in the art upon makingreference to the following detailed description and accompanyingdrawings in which preferred embodiments incorporating the principle ofthe present invention are shown by way of illustrative examples.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the overall arrangement of aconventional line redundant system to explain a conventional lineredundant scheme for ATM switching matrixes and the system therefor;

FIG. 2 is a block diagram showing the detailed arrangement of an ATMswitching matrix 2 at the time of APS operation in the arrangement shownin FIG. 1;

FIG. 3 is a block diagram showing the detailed arrangement of an ATMswitching matrix 3 at the time of APS operation in the arrangement shownin FIG. 1;

FIG. 4 is a block diagram showing the overall arrangement of a lineredundant system to explain a line redundant scheme for ATM switchingmatrixes and the system therefor according to an embodiment of thepresent invention;

FIG. 5 is a block diagram showing the detailed arrangement of an ATMswitching matrix 102 at the time of APS operation in the arrangementshown in FIG. 4;

FIG. 6 is a block diagram showing the detailed arrangement of an ATMswitching matrix 103 at the time of APS operation in the arrangementshown in FIG. 4;

FIG. 7 is a block diagram showing an example of path setting on thetransmission side of an APS line; and

FIG. 8 is a block diagram showing an example of path setting on thereception side of the APS line.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A preferred embodiment of the present invention will be described belowwith reference to FIGS. 4 to 8.

FIG. 4 shows an example of the overall arrangement of a system in a casewherein terminals 101 and 104 communicate with each other. Note that inthe present invention, as in the prior art, a description about thedetection of a trouble in the working route and the exchange of controlinformation with opposite ports by using K1/K2 bytes after thedetection, which are general techniques, will be omitted.

FIG. 5 shows the detailed arrangements a common switching fabric 113 a,0-system line accommodating section 130 a-0, and 1-system lineaccommodating section 140 a-1 in APS operation in an ATM switchingmatrix 102 in FIG. 4. The ATM switching matrix 102 is constituted by thecommon switching fabric 113 a, the 0-system line accommodating section130 a-0, the 1-system line accommodating section 140 a-1, and an OS 150a for controlling the ATM switching matrix 102. Each line accommodatingsection accommodates a plurality of lines (N lines for each line IF inFIG. 5). The common switching fabric 113 a is comprised of switch IFs117 a-1 to 117 a-n each of which accommodates one pair of 0-system lineaccommodating section 130 a-0 and 1-system line accommodating section140 a-1, a switch core 116 a for analyzing the header information of adata signal and distributing the information to each line accommodatingsection, and a switch control section 180 a. Each switch IF accommodatesa bridge 118 a which simultaneously distributes data from the switchcore 116 a to the 0-system line accommodating section 130 a-0 to the1-system line accommodating section 140 a-1. Note that the operation ofthe bridge 118 a is the same as that of the bridge 18 a in the priorart, and hence a description thereof will be omitted.

FIG. 6 shows the detailed arrangements of a common switching fabric 113b, 0-system line accommodating section 130 b-0, and 1-system lineaccommodating section 140 b-1 in APS operation in the ATM switchingmatrix 103 in FIG. 4. The arrangement of the embodiment of the presentinvention shown in FIG. 6 differs from that of the prior art shown inFIG. 3 in that a selector function is implemented, at the time ofswitching, for the data signals respectively input from the ATMswitching matrix 102 and ATM switching matrix 2 to an ATM switchingmatrix 103 and ATM switching matrix 3 through a protection route 115 andprotection route 15.

In the prior art shown in FIG. 3, the selector function is implementedon the common switching fabric 13 b side in the ATM switching matrix 3.In contrast, in the embodiment of the present invention shown in FIG. 6,the selector function is implemented at input ports 135 b-1 to 135 b-Nin the 0-system line accommodating section 130 b-0 and input ports 145b-1 to 145 b-N in the 1-system line accommodating section 140 b-1.

For example, the following are the details of the selector function in acase wherein after a trouble occurs in a working route 114, the datasignal received by the 0-system input port 135 b-1 through the workingroute 114 is cut off, and the data signal received by the 1-system inputport 145 b-1 through the protection route 115 is switched to be outputto the common switching fabric 113 b side.

The switching control function using K1/K2 bytes, an OS 150 b forcontrolling the ATM switching matrix 103, and a line control section fora 0-system line control section 131 b and 1-system line control section141 b cooperate with each other to determine a specific one of the0-system input port 135 b-1 and 1-system input port 145 b-1 from which adata signal should be output. When the occurrence of a trouble in theworking route 114 is detected, the OS 150 b and the line control sectioncooperate with each other to generate control signals so as to cut offthe data signal output from the input port 135 b-1 through the 0-systemline control section 131 b and output a data signal from the input port145 b-1 through the 1-system line control section 141 b.

That is, in the present invention, when the data signal bridged on thetransmission side is input and a trouble occurs in the working route,line switching control is performed such that the data signal outputfrom the 0-system input port of the pair of 0- and 1-system input portsis cut off, and the 1-system input port whose output has been cut off isallowed to output a data signal. In this manner, the selector functionis implemented.

The above selector function can be implemented by, for example, SONETframers that are originally provided for the input ports 135 b-1 to 135b-N and 145 b-1 to 145 b-N.

A SONET framer has a determination function of determining whether ornot to output a data signal from the SONET framer as well as a functionof assembling ATM cells into a SONET frame. The selector function cantherefore be implemented by using the determination function.

Note that not only SONET framers but also many commercially availableframers have the function of inhibiting an input data signal from beingoutput to the common switching fabric side. Therefore, in units otherthan ATM switching matrixes incorporating SONET framers, the datasignals input to various framers can be cut off (selected) for each portin a line accommodating section before the outputting of the signals tothe common switching fabric side by using the same function of theframers in the ports.

The arrangement of the present invention eliminates the necessity of theselectors 19 b (see FIG. 3) respectively arranged in the switch IFs 17b-1 to 17 b-n on the common switching fabric 13 b, and can simplify thehardware arrangement of the common switching fabric 113 b as indicatedby a switch IF 117 b-1 in FIG. 6. Note that the use of this function hasno influence on the remaining ports accommodated in the same system.

As described above, when it is necessary to perform line switching fromthe input port 135 b-1 in the working route in the 0-system lineaccommodating section 130 b-0 to the input port 145 b-1 in theprotection route in the 1-system line accommodating section 140 b-1,only the corresponding ports can be switched. That is, since theremaining input ports 135 b-2 (not shown) to 135 b-N during normaloperation in the 0-system line accommodating section 130 b-0 in whichthe reception circuit port 135 b-1 is accommodated are not forciblyswitched to the reception circuit ports 145 b-2 (not shown) to 145 b-Nin the 1-system line accommodating section 140 b-1, cell loss does noteasily occur in lines input to the input ports 135 b-2 (not shown) to135 b-N during normal operation.

To allow data signals to pass through the ATM switching matrixes 102 and103, path setting must be done in advance. This path setting isperformed such that 0- and 1-system line accommodating sections arepaired.

FIG. 7 shows an example of path setting on the transmission side of anAPS line. As is obvious from FIG. 7, a path is established from a inputport 155 a of a line accommodating section 112 a to a output port 134a-1 of the 0-system line accommodating section 130 a-0. On thetransmission side, a switch IF (not shown) in the common switchingfabric 113 a bridges (distributes) a data signal from the 0-system sideto output it to the 1-system line accommodating section 140 a-1 as well.Even if, therefore, the 0-system line accommodating section 130 a-0 isextracted, path setting for a switch core (not shown) in the commonswitching fabric 113 a is performed with respect to the 0-system lineaccommodating section 130 a-0. That is, in the 0-system lineaccommodating section 130 a-0, path setting is performed from the switchcore to the output port 134 a-1. In addition, in the 1-system lineaccommodating section 140 a-1 to which the data signal from the 0-systemside is bridged, path setting is also performed for a input port 144 a-1from the switch core (not shown).

FIG. 8 shows an example of path setting on the reception side of an APSline. As is obvious from FIG. 8, a path is established from the inputport 135 b-1 of the 0-system line accommodating section 130 b-0 to aoutput port 154 b of a line accommodating section 112 b. At the sametime, a path is established from the input port 145 b-1 of the 1-systemline accommodating section 140 b-1, which pairs up with the above port,to the output port 154 b of the line accommodating section 112 b.

As described above, path setting is always performed on both thetransmission and reception sides of line accommodating section pairs.Note that when one of an APS line accommodating section pair isextracted, and the other is inserted, the OS that controls the ATMswitching matrix performs path setting for the inserted lineaccommodating section again by using path setting for a lineaccommodating section that is not extracted.

In the above description, an ATM switching matrix is used as a switchingmatrix, and an ATM cell is used as a data signal. However, the switchingmatrix and data signal are not limited to those described above as longas they comply with the APS specifications. For example, the presentinvention can also be applied to a line redundant scheme in an IP overSONET system which directly transmits IP packets through a SONETnetwork.

1-8. (canceled)
 9. A method comprising: receiving, by a first port, afirst data signal; one of forwarding the received first data signal to anetwork device or cutting-off forwarding of the received first datasignal to the network device using a first function of a first framerimplemented at the first port; receiving, by a second port, a seconddata signal, the second port being different than the first port; one offorwarding the received second data signal to the network device orcutting-off forwarding of the received second data signal to the networkdevice using a second function of a second framer implemented at thesecond port, the second function being different than the firstfunction.
 10. The method of claim 9, where the one of forwarding thereceived first data signal to the network device or cutting-offforwarding of the received first data signal to the network deviceincludes: forwarding the received first data signal to the networkdevice, when the first data signal is being received normally; andcutting-off forwarding of the received first data signal to the networkdevice, when the first data signal is being received abnormally.
 11. Themethod of claim 9, where the one of forwarding the received second datasignal to the network device or cutting-off forwarding of the receivedsecond data signal to the network device includes: forwarding thereceived second data signal to the network device, when the first datasignal is being received abnormally; and cutting-off forwarding of thereceived second data signal to the network device, when the first datasignal is being received normally.
 12. The method of claim 9, furthercomprising: generating at least one first control signal; cutting-off,based on the generated at least one first control signal, forwarding ofthe received first data signal to the network device; and forwarding,based on the generated at least one first control signal, the receivedsecond data signal to the network device.
 13. The method of claim 12,where the received first data signal is received via a first route, themethod further comprising: detecting a failure in the first route; andgenerating the at least one first control signal based on the detecting.14. The method of claim 12, further comprising: generating at least onesecond control signal; cutting-off, based on the generated at least onesecond control signal, forwarding of the received second data signal tothe network device; and forwarding, based on the generated at least onesecond control signal, the received first data signal to the networkdevice.
 15. The method of claim 14, where the generated at least onesecond control signal is based on the first route functioning without afailure.
 16. The method of claim 9, where the network device includes anAsynchronous Transfer Mode (ATM) switching matrix, and where at leastone of the received first data signal or the received second data signalcomprises an ATM cell.
 17. The method of claim 9, further comprising:performing path setting; and forwarding, based on the performed pathsetting, at least one of the received first data signal or the receivedsecond data signal.
 18. A system comprising: a device to: receive, at afirst port, a first data signal; receive, at a second port, a seconddata signal, where the first port is different than the second port; oneof forward the received first data signal in the device or cut-offforwarding of the received first data signal in the device using a firstfunction of a first framer implemented at the first port; and one offorward the received second data signal in the device or cut-offforwarding of the received second data signal in the device using asecond function of a second framer implemented at the second port, wherethe second function is different than the first function.
 19. The systemof claim 18, where the device includes an Asynchronous Transfer Mode(ATM) switching matrix, and where at least one of the received firstdata signal or the received second data signal comprises an ATM cell.20. The system of claim 18, where, when one of forwarding the receivedfirst data signal in the device or cutting-off forwarding of thereceived first data signal in the device, the device is to: forward thereceived first data signal in the device when the first data signal isbeing received normally via a first route; and cut-off forwarding of thereceived first data signal in the device when the first data signal isbeing received abnormally via the first route.
 21. The system of claim20, where the device is further to: generate one or more signals basedon a detected failure in the first route, forward, based on thegenerated one or more signals, the received second data signal, andcut-off, based on the generated one or more signals, forwarding of thereceived first data signal.
 22. The system of claim 18, where, when oneof forwarding the received second data signal in the device orcutting-off forwarding of the received second data signal in the device,the device is to: forward the received second data signal in the devicewhen the first data signal is being received abnormally via a firstroute; and cut-off forwarding of the received second data signal in thedevice when the first data signal is being received normally via thefirst route.
 23. The system of claim 18, where the device is further to:receive, at a third port, a third data signal, forward, using a functionof a third framer implemented at the third port, the received third datasignal in the device, receive, at a fourth port, a fourth data signal,and cut-off, using a function of a fourth framer implemented at thefourth port, forwarding of the received fourth data signal in thedevice.
 24. A device comprising: a first input port to receive a firstdata signal; a first framer, implemented at the first input port, to:one of forward the received first data signal in the device or cut-offforwarding of the received first data signal in the device using a firstfunction; a second, different input port to receive a second datasignal; and a second framer, implemented at the second input port, to:one of forward the received second data signal in the device or cut-offforwarding of the received second data signal in the device using asecond, different function.
 25. The device of claim 24, where thereceived first data signal is received via a first route, the devicefurther comprising: a component to generate at least one signal based ona failure of the first route, where, based on the generated at least onesignal, the first framer is to cut-off forwarding of the received firstdata signal, and the second framer is to forward the received seconddata signal.
 26. The device of claim 25, where the component is togenerate at least one second signal, and where, based on the generatedat least one second signal, the first framer is to forward the receivedfirst data signal, and the second framer is to cut-off forwarding of thereceived second data signal.
 27. The device of claim 24, where thedevice comprises a switching matrix.
 28. The device of claim 24, thedevice further comprising: a third framer to: cut-off forwarding, usinga third function of the third framer, a third data signal in the device,when the third data signal is being received abnormally; and a fourthframer to: forward, using a fourth function of the fourth framer, afourth data signal in the device, when the third data signal is beingreceived abnormally.
 29. The device of claim 28, where the third frameris to forward, using the third function and based on the third datasignal being received normally, the third data signal in the device, andwhere the fourth framer is to cut-off, using the fourth function andbased on the third data signal being received normally, forwarding ofthe fourth data signal in the device.